1. PIN ASSIGNMENT FOR TYSSO MCR Series (TTL)
| PIN NO. | SIGNAL NAME | WIRE COLOR |
SINGLE TRACK CONNECTOR FOR 5 PINS | 1 2 3 4 5 | /RDP /RCP /CLS +5V GND | YELLOW ORANGE RED BROWN BLACK |
SINGLE TRACK CONNECTOR FOR 7 PINS | 1 2 3 4 5 6 7 | +5V GND /RDP ------ /RCP ------ /CLS | BLACK BROWN RED ORANGE YELLOW GREEN BLUE |
DUAL TRACK CONNECTOR | 1 2 3 4 5 6 7 | +5V GND /RDP (TRACK 2) /RDP (TRACK 1/3) /RCP (TRACK 2) /RCP (TRACK 1/3) /CLS | BLACK BROWN RED ORANGE YELLOW GREEN BLUE |
THREE TRACK CONNECTOR | 1 2 3 4 5 6 7 8 9 10 | +5V GND /CLS 123 --------------- /RCP (TRACK 1) /RCP (TRACK 2) /RDP (TRACK 1) /RDP (TRACK 2) /RCP (TRACK 3) /RDP (TRACK 3) | BLACK BROWN RED N.C. YELLOW GREEN BLUE VIOLET GRAY WHITE |
2. MCR – Signal Timing Chart
NOTICE:
(1) NACT=(NACT1)LOGIC-OR(NACT2).LOGIC-OR(NACT3)
(2) Tim：Time from card-in to signal ”CARD ACTIVE” going low.
<Options > 1/Tin=4-bit for NACT at NACTS = low.
<Denotations> 1/Card-in refers to first active bit of magnetic signal.
2/Tin=4-bit for NACT at NACTS=low
(3) Tout：Time from card-out to signal “CARD ACTIVE” going high.
(Tout=40.9ms at CLK=8MHZ).
(4) Tdkn：Time from signal “DATA READY” to signal “CLOCK LATCH”
(Tdkn=6.127us at CLK=8MHZ).
(5) Tdkw：Time from signal “DATA READY” to signal “CLOCK LATCH”
(Tdkw is fuzzy controlled. When DAT transition gets faster, the Tdkw Gets shorter.)
3. Slot-Housing Dimensions：10cm Length
4. Slot-Housing Dimensions：9.0 cm Length
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